TC511002P-12中文资料东芝数据手册PDF规格书

DESCRIPTION

The TC511002P/J/Z is the new generation dynamic

RAM organized 1,048,576 words by 1 bit. The TC511002

P/J/Z utilizes TOSHIBA's CMOS Silicon gate process

technology as well as advanced circuit techniques to

provide wide operating margins, both internally and to

the system user. Multiplexed address inputs permit the

TC511002P/J/Z to be packaged in a standard 18 pin

plastic DIP, 26/20 pin plastic SOJ and 20/19 pin plastic

ZIP. The package size provides system bit densities and

is compatible with widely available automated testing

and insertion equipment. System oriented features

include single power supply of 5V ± 10 tolerance,

direct interfacing capability with high performance logic

families such as Schottky TTL. Test Mode function is

implemented from Revision C.

FEATURES

1,048,576 word by 1 bit organization

• Fast access time and cycle time

THAC

TAA

ICAC

TAC

tsc

RAS Access Time

Column Address Access

Time

CS Access Time

Cycle Time

Static Column Mode Cycle

Time

TC511002P/J/Z-85-10-12

85ns 100ns 120ns

45ns 50ns 60ns

25ns

25ns

30ns

165ns 190ns 220ns

50ns 55ns 65ns

Sincle power supply of 5V ± 10 with a built-in VBB

generator

Low Power

385mW MAX. Operating (TC511002P/J/Z-85)

330mW MAX. Operating (TC511002P/J/Z-10)

275mW MAX. Operating (TC511002P/J/Z-12)

5.5mW MAX. Standby

Output unlatched at cycle end allows two-dimensional

chip selection

Common I/O capability

Read-Modify-Write, CS before RAS refresh, RAS-only

refresh, Hidden refresh, Static Column Mode and Test

Mode capability.

• All inputs and output TTL compatible

512 refresh cycles/8ms

● Package

Plastic DIP: TC511002P

Plastic SOJ: TC511002J

Plastic ZIP: TC511002Z