TC511000P-12中文资料东芝数据手册PDF规格书

DESCRIPTION

The TC511000P/J/Z is the new generation dynamic

RAM organized 1,048,576 words by 1 bit. The

TC511000P/J/Z utilizes TOSHIBA's CMOS Silicon gate

process technology as well as advanced circuit techniques

to provide wide operating margins, both internally and to

the system user. Multiplexed address inputs permit the

TC511000P/J/Z to be packaged in a standard 18 pin

plastic DIP, 26/20 pin plastic SOJ and 20/19 pin plastic

ZIP. The package size provides high system bit densities

and is compatible with widely available automated testing

and insertion equipment. System oriented features

include single power supply of 5V ± 10 tolerance, direct

interfacing capability with high performance logic

families such as Schottky TTL. Test Mode function is

implemented from Revision C.

FEATURES

1,048,576 word by 1 bit organization

Fast access time and cycle time

TRAC RAS Access Time

Column Address Access

Time

TAA

tCAC CAS Access Time

tRc Cycle Time

tpc

Fast Page Mode Cycle

Time

TC511000P/J/Z-85-10-12

100 ns

50 ns

25 ns

190 ns

55 ns

85 ns

45 ns

25 ns

165 ns

50 ns

120 ns

60 ns

30 ns

220 ns

70 ns

Single power supply of 5V ± 10 with a built-in VBB

generator

Low Power

385mW MAX. Operating (TC511000P/J/Z-85)

330mW MAX. Operating (TC511000P/J/Z-10)

275mW MAX. Operating (TC511000P/J/Z-12)

5.5mW MAX. Standby

Output unlatched at cycle end allows two-dimensional

chip selection

Common 1/O capability using EARLY WRITE

operation

Read-Modify-Write, CAS before RAS refresh, RAS-

only refresh, Hidden refresh, Fast Page Mode and Test

Mode capability

All inputs and output TTL compatible

• 512 refresh cycles/8 ms

Package Plastic DIP: TC511000P

Plastic SOJ: TC511000J

Plastic ZIP TC511000Z