TB5T1DW集成电路（IC）的驱动器接收器收发器规格书PDF中文资料

TB5T1DW属于集成电路（IC）的驱动器接收器收发器。由德州仪器制造生产的TB5T1DW驱动器，接收器，收发器该系列产品的主要功能是提供必需的硬件资源，以通过延长电缆或印制线进行通信。确切的功能会因所采用的通信协议而异，可能包括诸如瞬态抑制之类的功能，这些功能对于通信用途可能并非绝对必要，但对于可能的使用环境却是明智之选。

1FEATURES

· Functional Replacement for the Agere BTF1A

· Driver Features

. Third-State Logic Low Output

. ESD Protection HBM > 3 kV, CDM > 2 kV

. No Line Loading when VCC = 0

. Capable of Driving 50-Ω loads

. 2.0-ns Maximum Propagation Delay

. 0.2-ns Output Skew (typical)

· Receiver Features

. High-Input Impedance Approximately 8 kΩ

. 4.0-ns Maximum Propagation Delay

. 50-mV Hysteresis

. Slew Rate Limited (1 ns min 80% to 20%)

. ESD Protection HBM > 3 kV, CDM > 2 kV

. -1.1-V to 7.1-V Input Voltage Range

· Common Device Features

. Common Enable for Each Driver/Receiver

Pair

. Operating Temperature Range: -40°C to

85°C

. Single 5.0 V ± 10% Supply

. Available in Gull-Wing SOIC (JEDEC

MS-013, DW) and SOIC (D) Package

DESCRIPTION

The TB5T1 device is a dual differential driver/receiver

circuit that transmits and receives digital data over

balanced transmission lines. The dual drivers

translate input TTL logic levels to differential

pseudo-ECL output levels. The dual receivers convert

differential-input logic levels to TTL output levels.

Each driver or receiver pair has its own common

enable control allowing serial data and a control clock

to be transmitted and received on a single integrated

circuit. The TB5T1 requires the customer to supply

termination resistors on the circuit board.

The power-down loading characteristics of the receiver input circuit are approximately 8 kΩ relative

to the power supplies; hence, it does not load the

transmission line when the circuit is powered down.

In circuits with termination resistors, the line remains

impedance- matched when the circuit is powered down. The driver does not load the line when it is

powered down.

All devices are characterized for operation from -40°C

to 85°C.

The logic inputs of this device include internal pull-up

resistors of approximately 40 kΩ that are connected

to VCC to ensure a logical high level input if the inputs

are open circuited.