TAMC863-DOC中文资料TEWS数据手册PDF规格书

Application Information

The TAMC863 is a standard single Mid-Size/Full-Size AMC.1 compliant module with four high speed serial data communication channels.

The serial communication controller is implemented in FPGA logic, along with a bus master capable PCI interface, guaranteeing long term availability with the option to implement additional functions in the future. The FPGA is connected to the PCI Express interface via a PCI Express to PCI bridge.

Each channel has a receive and a transmit FIFO of 512 long words (32 bit) per channel for high data throughput.

Data transfer on the PCI bus is handled via TAMC863 initiated DMA cycles with minimum host/CPU intervention.

Several serial communication protocols are supported by each channel, such as asynchronous, isochronous, synchronous and HDLC mode.

A 14.7456 MHz oscillator provides standard asynchronous baud rates. An additional 24 MHz oscillator is provided for other baud rates. A 10 MHz oscillator is used for the synchronous baud rate of 10 Mbit/s.

Each channel also provides various interrupt sources, generated on INTA. The interrupt sources can be enabled or disabled individually.

Multiprotocol transceivers are used for the line interface. The physical interface is selectable by software, individually for each channel as EIA-232, EIA-422, EIA-449, EIA-530, EIA-530A, V.35, V.36 or X.21.

The following signals are provided by the TAMC863 for each channel at the front I/O connector: Receive Data (RxD +/-), Transmit Data (TxD +/-), Receive Clock (RxC +/-), Transmit Clock (TxC +/-), Ready-To-Send (RTS +/-), Clear-To-Send (CTS +/-), Carrier-Detect (CD +/-) and GND. Additionally, serial channel 3 provides Data-Set-Ready (DSR3 +/-) and Data-Terminal-Ready (DTR3 +/-).