TAMC640-13R中文资料TEWS数据手册PDF规格书

Application Information

The TAMC640 is a standard single Mid-Size or Full-Size AMC module providing a user configurable Virtex-5 FPGA. The integrated PCIe Endpoint Block of the Virtex-5 can be used to build an x1, x4 or x8 PCIe link via AMC Port 4-11. The implementation of other protocols like SRIO or XAUI is also possible. AMC Ports 0 & 1, commonly used for Gigabit Ethernet, are also connected to the FPGA. The integrated Gigabit Ethernet MACs of the Virtex-5 allow fast and easy protocol implementation.

To allow direct board-to-board communication, AMC Ports 12-17 are connected to Virtex-5 I/Os, allowing AC-coupled LVDS communication with a port speed up to 1.0Gb/sec.

For flexible I/O solutions the TAMC640 provides a VITA 57.1 high pin count FMC Module slot, allowing active and passive signal conditioning. All FMC I/O lines are directly connected to the FPGA, which maintains the flexibility of the Select I/O technology of the Virtex-5 FPGA.

In addition, the FPGA is connected to the following external memories:

• two banks of DDR2 DRAM (up to 128 M x 16 (256 MB) each)

• one bank of QDR-II SRAM (up to 4 M x 18 (8 MB))

Multiple clocks from the AMC-interface, the FMC and from on-board sources are supplied to the FPGA.

The FPGA is configured by a flash device, which is in-system programmable and able to store multiple code versions.

The TAMC640 supports encrypted FPGA bitstream usage. Encrypted FPGA bitstreams cannot be copied or reverse engineered, securing your intellectual property.

The IPMI Connectivity Records located inside the Module Management Controller (MMC) can be modified by the customer (e.g. via IPMI), to adapt to the different possible communication protocols (PCIe, SRIO, XAUI, ...).

User applications for the TAMC640 require the full ISE Foundation software, which must be purchased from Xilinx.

The Engineering Documentation TAMC640-ED includes all information needed for customer specific FPGA programming. The FPGA Development Kit TAMC640-FDK includes the engineering documentation, ucf-files with all necessary pin assignments and basic timing constraints, and a well documented VHDL example application. This example application is called TPLD002 (Tews Programmable Logic Design) and covers the main functionalities of the TAMC640 like DMA capable PCIe endpoint with interrupt support, register mapping, DDR2 and QDR-II memory access and basic I/O to the FMC slot. It comes as a Xilinx ISE project with source code and as a ready-to-download bitstream. It is the basis for fast and reliable customer application development, and can significantly reduce time to market.

Software support for the TPLD002 is available for all major operating systems.

In-circuit programming and debugging of the FPGA design (e.g. using Xilinx “ChipScope”) is supported. The Program and Debug Box TA900 allows access to the module while it is inserted in a system. It provides access to the module's JTAG Chain, the UART of the on-board Module Management Controller (MMC) and to two user pins of the Virtex-5 FPGA. If a UART core is implemented in the FPGA, serial communication via the TA900 is possible.

The TA900 can be accessed by USB 2.0 and by a 14-pin JTAG Header (e.g. for connecting a Xilinx Platform Cable).

For First-Time-Buyers the TA900 and the TAMC640-ED or TAMC640-FDK is recommended.