STANDARD TRIACS

IT(RMS) = 25A VDRM = 400V to 800V High surge current capability

文件：306.22 Kbytes 页数：5 Pages

STMICROELECTRONICS

意法半导体

STANDARD TRIACS

IT(RMS) = 25A VDRM = 400V to 800V High surge current capability

文件：306.22 Kbytes 页数：5 Pages

STMICROELECTRONICS

意法半导体

QorIQ, 1xCPU 64-Bit Pwr Arch, 1.4GHz, DDR3L/4, PCIe, 1/10GbE, HW Accel, SEC, 0 to 105C, 19x19 pkg

The QorIQ® dual-core T1024 and T1023 and single-core T1014 and T1013 communications processors combine 64-bit cores, built on Power Architecture® technology, with high-performance Data Path Acceleration Architecture (DPAA) and network peripheral bus interfaces required networking, telecommunications Core Complex• Single and dual e5500 cores, built on Power Architecture technology\n• Up to 1.4 GHz with 64-bit ISA support\n• Three levels of instructions: user, supervisor, hypervisor\n• Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture\n• 256 KB backside L2 cach;

恩XP

QorIQ, 1xCPU 64-Bit Pwr Arch, 1.4GHz, DDR3L/4, PCIe, 1/10GbE, HW Accel, 0 to 105C, 19x19 pkg

The QorIQ® dual-core T1024 and T1023 and single-core T1014 and T1013 communications processors combine 64-bit cores, built on Power Architecture® technology, with high-performance Data Path Acceleration Architecture (DPAA) and network peripheral bus interfaces required networking, telecommunications Core Complex• Single and dual e5500 cores, built on Power Architecture technology\n• Up to 1.4 GHz with 64-bit ISA support\n• Three levels of instructions: user, supervisor, hypervisor\n• Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture\n• 256 KB backside L2 cach;

恩XP

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The QorIQ® dual-core T1024 and T1023 and single-core T1014 and T1013 communications processors combine 64-bit cores, built on Power Architecture® technology, with high-performance Data Path Acceleration Architecture (DPAA) and network peripheral bus interfaces required networking, telecommunications Core Complex• Single and dual e5500 cores, built on Power Architecture technology\n• Three levels of instructions: user, supervisor, hypervisor\n• 256 KB backside L2 cache;

恩XP