SY88053CL中文资料limiting post amplifier is designed for use in fiber-optic receivers数据手册Microchip规格书

描述 Description

The SY88053CL limiting post amplifier is designed for use in fiber-optic receivers for multi-rate applications from 1.0625Gbps to 12.5Gbps.

The SY88053CL contains a high-bandwidth, high-sensitivity input stage with user-programmable, wide-range SD assert/LOS de-assert threshold levels, which enables optimized system reach. Typically, 4dB of electrical hysteresis is provided to minimize LOS or SD chattering caused by noisy input signals. A logic level control pin is provided to enable user selection of an open-collector, TTL-compatible LOS or SD status indication signal with an external 5kΩ to 10kΩ pull-up resistor.

The SY88053CL provides fast SD assert and LOS de-assert times over the entire differential input voltage range of 5mVPP to 1800mVPP.

The SY88053CL input stage also provides a user-adjustable decision threshold circuit to optimize BER in noisy applications such as WDM, where EDFA and Raman amplifiers contribute uneven noise levels. By applying an external control voltage, the decision threshold can typically be adjusted from 30% to 70% from the nominal 50% threshold when the circuit is disabled.

The SY88053CL provides integrated 50Ω input and output impedances to optimize the high-speed signal paths and reduce component count. The post amplifier outputs have user-selectable polarity inversion control to simplify PCB layout. A TTL-compatible JAM input is provided to enable a SQUELCH function by feeding back the LOS or SD signal. The JAM input disables only the post amplifier output.

The SY88053CL operates from a single +3.3V power supply, over temperatures ranging from –40°C to +85°C.

To request the datasheet, please email us at tcg_help@microchip.com

For product comparison, please consider:SY88073L

特性 Features

Multi-rate operation from 1.0625Gbps to 12.5Gbps
Adjustable decision threshold level for offset compensation or BER optimization
Wide differential input range (5mVPP to 1800mVPP)
Wide SD de-assert or LOS assert threshold range3mVPP to 30mVPP
4dB typical electrical hysteresis
Fast SD assert and LOS de-assert times75ns typical; 120ns maximum
Selectable LOS or SD status signal indicator
Selectable RXOUT+/RXOUT- polarity inversion
TTL-compatible JAM input with internal pull-up
Low-noise CML data inputs with integrated 50Ω termination impedance to internal reference VREF
Low-noise CML data outputs with integrated 50Ω termination impedance25ps typical rise/fall times
Wide range power supply: 3.3V ±10%
Industrial temperature range: -40°C to +85°C
Available in a tiny 3mm x 3mm QFN package