SY69753AL中文资料Clock and Data Recovery数据手册Microchip规格书

描述 Description

The SY69753AL is a complete Clock Recovery and Data Retiming integrated circuit for OC-3/STS-3 applications at 155Mbps NRZ. The device is ideally suited for SONET/SDH/ATM applications and other high-speed data transmission systems.Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference.The SY69753AL also includes a link fault detection circuit.

特性 Features

3.3V power supply
SONET/SDH/ATM compatible
Clock and data recovery for 125Mbps/155Mbps NRZ data stream
Two on-chip PLLs: one for clock generation and another for clock recovery
Selectable reference frequencies
Differential PECL high-speed serial I/O
Line receiver input: no external buffering needed
Link fault indication
100k ECL compatible I/O
Industrial temperature range (-40°C to +85°C)
Lower power: fully compatible with Micrel's SY87701V, but with 30% less power
Available in 32-pin ePad-TQFP

简介

SY69753AL属于集成电路（IC）的应用特定时钟/定时。由制造生产的SY69753AL应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。