SY10H351JCTR中文资料麦瑞半导体数据手册PDF规格书

DESCRIPTION

The SY10H351 is a quad translator for interfacing data between a saturated logic selection and the PECL section of digital systems when only a +5.0V VDC power supply is available. The SY10H351 has TTL/NMOS compatible inputs and PECL complementary open-emitter outputs that allow use as an inverting/non-inverting translator or as a differential line driver. When the common strobe input is at a low logic level, it forces all true outputs to the PECL low logic state (≈ +3.2V) and all inverting outputs to the PECL high logic state (≈ 4.1V).

The SY10H351 can also be used with the SY10H350 to transmit and receive TTL/NMOS information differentially via balanced twisted pair lines.

FEATURES

■ Single 5V power supply

■ All VCC pins isolated on chip

■ Differentially drive balanced lines

■ tPD 1.3ns typical

■ Fully compatible with MC10H351

■ Available in 20-pin PLCC package