DESCRIPTION

The SY10EP51V is a D flip-flop with reset and differential clock. The device is pin and functionally equivalent to the EL51 device.

The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when CLK is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK. The differential clock inputs of the EP51V allow the device to be used as a negative edge triggered flip-flop.

FEATURES

■ 3.3V and 5V power supply options

■ 320ps typical propagation delay

■ Maximum frequency > 3GHz typical

■ 75KΩ internal input pulldown resistor

■ Transistor count: 143

■ Available in 8-Pin (3mmx3mm) MSOP, SOIC and MLF® (2mmx2mm) packages