SY10ELT23ZCTR中文资料麦瑞半导体数据手册PDF规格书

DESCRIPTION

The SY10/100ELT23 are dual differential PECL-to-TTL translators. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and the low skew dual gate design of the ELT23 makes it ideal for applications which require the translation of a clock and a data signal.

The ELT23 is available in both ECL standards: the 10ELT is compatible with positive ECL 10H logic levels, while the 100ELT is compatible with positive ECL 100K logic levels.

FEATURES

■ 3.0ns typical propagation delay

■ <500ps typical output-to-output skew

■ Differential PECL inputs

■ 24mA TTL outputs

■ Flow-through pinouts

■ Internal input 50kΩ pulldown resistors

■ Available in 8-pin SOIC package