SY10E175JCTR中文资料麦瑞半导体数据手册PDF规格书

DESCRIPTION

The SY10/100E175 are 9-bit latches. They also feature a tenth latched output (ODDPAR) which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH).

The E175 can also be used to generate byte parity by using D8 as the parity-type select (L = even parity, H = odd parity) and using ODDPAR as the byte parity output.

The LEN pin latches the data when asserted with a logical high and makes the latch transparent when placed at a logic low level.

FEATURES

■ 9-bit latch

■ Extended 100E VEE range of –4.2V to –5.5V

■ Parity detection/generation

■ 800ps max. D to Output

■ Reset

■ Internal 75KΩ input pull-down resistors

■ Fully compatible with Motorola MC10E/100E175

■ Available in 28-pin PLCC package