(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP

DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by

文件：73.62 Kbytes 页数：4 Pages

Micrel

麦瑞半导体

(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP

DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by

文件：73.62 Kbytes 页数：4 Pages

Micrel

麦瑞半导体

(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP

文件：483.53 Kbytes 页数：5 Pages

Micrel

麦瑞半导体

(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP

DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by

文件：73.62 Kbytes 页数：4 Pages

Micrel

麦瑞半导体

(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP

DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by

文件：73.62 Kbytes 页数：4 Pages

Micrel

麦瑞半导体

(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP

文件：483.53 Kbytes 页数：5 Pages

Micrel

麦瑞半导体

Package：20-SOIC（0.295"，7.50mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLOCK GEN 3.3V/5V 20-SOIC

Microchip

微芯科技

Package：20-SOIC（0.295"，7.50mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLOCK GEN 3.3V/5V 20-SOIC

Microchip

微芯科技