SY100S811JCTR中文资料麦瑞半导体数据手册PDF规格书

DESCRIPTION

The SY100S811 is a low skew 1-to-9 PECL differential driver designed for clock distribution in new, high performance PECL systems. It accepts either a PECL clock input or a TTL input by using the TTL enable pin TEN. When the TTL enable pin is HIGH, the TTL input is enabled and the PECL input is disabled. When the enable pin is set LOW, the TTL input is disabled and the PECL input is enabled.

FEATURES

■ PECL version of popular ECLinPS E111

■ Low skew

■ Guaranteed skew spec

■ VBB output

■ TTL enable input

■ Selectable TTL or PECL clock input

■ Single +5V supply

■ Differential internal design

■ Similar pin configuration to E111

■ PECL I/O fully compatible with industry standard

■ Internal 75KΩ PECL input pull-down resistors

■ Available in 28-pin PLCC and SOIC packages