DUAL PARITY CHECKER/GENERATOR

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DUAL PARITY CHECKER/ GENERATOR

DESCRIPTION The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each and the parity output is at a logic LOW when an even number of inputs are at a logic HIGH. In each group, one of the n

文件：99.86 Kbytes 页数：5 Pages

MICREL

麦瑞半导体

DUAL PARITY CHECKER/GENERATOR

文件：89.23 Kbytes 页数：6 Pages

MICREL

麦瑞半导体

DUAL PARITY CHECKER/ GENERATOR

文件：82.24 Kbytes 页数：4 Pages

MICREL

麦瑞半导体