SY100S355中文资料Multiplexers Products数据手册Microchip规格书

描述 Description

The SY100S355 offers four transparent latches with differential outputs and is designed for use in high-performance ECL systems. The Select inputs (S0, S1) select one of the two sources of input data (D0 or D1) to the latch. The Select inputs can also force the outputs to a logic LOW when the latch is in the transparent mode. The latches are in the transparent mode when both Enables (E1, E2) are at a logic LOW state. In the transparent mode, the Select inputs can pass an input logic HIGH from D0 or D1 to the output.If the Select inputs are tied together, then input data from either D0 or D1 is always passed through. A rising edge on either Enable input will latch the outputs with the most recent data at the latch inputs being stored. The Master Reset (MR) input overrides all other inputs and takes the Q outputs to a logic LOW. The inputs on this device have 75K pull-down resistors.

特性 Features

·Max. propagation delay of 1100ps
·Max. enable to output delay of 1400ps
·IEE min. of -80mA
·Industry standard 100K ECL levels
·Extended supply voltage option:
·VEE= -4.2V to -5.5V
·Voltage and temperature compensation for improved noise immunity
·Internal 75K input pull-down resistors
·50% faster than National or Signetics
·Function and pinout compatible with National and Signetics F100K
·Available in 28-pin PLCC package

简介

SY100S355属于集成电路（IC）的锁存器。由制造生产的SY100S355锁存器锁存器是类似于触发器的基本数字存储设备，但是不同之处在于，在锁存使能（或类似命名）信号处于有效逻辑状态的任何时间，保持的逻辑状态都可以改变。“透明”锁存器还允许设备输出在锁存使能信号有效时反映输入的当前状态，而相反的是，状态仅在保持状态已固定时改变。