SY100EP195V数据手册集成电路（IC）的延迟线规格书PDF

描述 Description

The SY100EP195V is a programmable delay line, varying the time a logic signal takes to traverse from IN to Q. This delay can vary from about 2.2ns to about 12.2ns. The input can be PECL, LVPECL, NECL, or LVNECL.The delay varies in discrete steps based on a control word presented to SY100EP195V. The 10-bit width of this latched control register allows for delay increments of approximately 10ps.An eleventh control bit allows the cascading of multiple SY100EP195V devices, for a wider delay range. Each additional SY100EP195V effectively doubles the delay range available.For maximum flexibility, the control register interface accepts CMOS or TTL level signals, as well as the input level at the IN± pins.

特性 Features

• Pin-for-pin, plug-in compatible to the ON Semiconductor MC100EP195
• Maximum frequency >2.5GHz
• Programmable range: 2.2ns to 12.2ns
• 10ps increments
• PECL mode operating range: VCC = 3.0V to 5.5V with VEE = 0V
• NECL mode operating range: VCC = 0V with VEE = –3.0V to –5.5V
• Open input default state
• Safety clamp on inputs
• A logic high on the /EN pin will force Q to logic low
• D[0:10] can accept either ECL, CMOS, or TTL inputs
• VBB output reference voltage
• Available in a 32-pin TQFP package

简介

SY100EP195V属于集成电路（IC）的延迟线。由制造生产的SY100EP195V延迟线时钟延迟线产品族中的产品属于数字器件，用于在数字信号中引入时间延迟，以便将提交给器件输入的信号跃迁，经过某一已知时间之后在输出端复现。它们常用于高速数字系统，以校正或补偿不同信号路径之间的信号传播时间的偏差。这些器件可用于产生固定、可选或可变持续时间的延迟。