SY100ELT22ZCTR中文资料麦瑞半导体数据手册PDF规格书

DESCRIPTION

The SY10/100ELT22 are dual TTL-to-differential PECL translators. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the tranlation of a clock and a data signal.

The ELT22 is available in both ECL standards: the 10ELT is compatible with positive ECL 10H logic levels, while the 100ELT is compatible with positive ECL 100K logic levels.

FEATURES

■ 300ps typical propagation delay

■ <100ps output-to-output skew

■ Differential PECL outputs

■ PNP TTL inputs for minimal loading

■ Flow-through pinouts

■ Available in 8-pin SOIC package