SY100ELT20VZCTR中文资料麦瑞半导体数据手册PDF规格书

DESCRIPTION

The SY10/100ELT20V is a single TTL-to-differential PECL translator. Because PECL (Positive ECL) levels are used, either +5V or +3.3V and ground are required. The small outline 8-lead SOIC package and low skew single gate design make the ELT20V ideal for applications that require the translation of a clock or data signal where minimal space, low power, and low cost are critical.

The ELT20V is available in both ECL standards: the 10ELT is compatible with positive ECL 10H logic levels, while the 100ELT is compatible with positive ECL 100K logic levels.

FEATURES

■ 3.3V and 5V power supply options

■ 300ps typical propagation delay

■ Low power

■ Differential PECL output

■ PNP TTL input for minimal loading

■ Flow-through pinouts

■ Available in 8-pin SOIC package and in die form