SY100EL33L

3.3V ECL ÷ 4 Divider;

The SY100EL33L are integrated ÷4 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL33L only; the VBB output has limited current sink and source capability.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset input allows for the synchronization of multiple EL33Ls in a system.\n\n \n\n

SY100EL33L

5V/3.3V 첨 4 DIVIDER

SY100EL33LZC

5V/3.3V 첨 4 DIVIDER

DESCRIPTION TheSY10/100EL33/Lareintegrated÷4dividers.ThedifferentialclockinputsandtheVBBallowadifferential,single-endedorAC-coupledinterfacetothedevice.Ifused,theVBBoutputshouldbebypassedtogroundwitha0.01µFcapacitor.AlsonotethattheVBBisdesignedtobeu

SY100EL33LZCTR

5V/3.3V 첨 4 DIVIDER

DESCRIPTION TheSY10/100EL33/Lareintegrated÷4dividers.ThedifferentialclockinputsandtheVBBallowadifferential,single-endedorAC-coupledinterfacetothedevice.Ifused,theVBBoutputshouldbebypassedtogroundwitha0.01µFcapacitor.AlsonotethattheVBBisdesignedtobeu

SY100EL33LZC

5V/3.3V 첨 4 DIVIDER

SY100EL33LZCTR

5V/3.3V 첨 4 DIVIDER

SY100EL33LZG

5V/3.3V 첨 4 DIVIDER

SY100EL33LZGTR

5V/3.3V 첨 4 DIVIDER

SY100EL33LZI

5V/3.3V 첨 4 DIVIDER

SY100EL33LZITR

5V/3.3V 첨 4 DIVIDER