SY100EL33数据手册集成电路（IC）的计数器除法器规格书PDF

描述 Description

The SY100EL33L are integrated ÷4 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL33L only; the VBB output has limited current sink and source capability.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset input allows for the synchronization of multiple EL33Ls in a system.

特性 Features

·3.3V and 5V power supply options
·650ps propagation delay
·4.0GHz toggle frequency
·High bandwidth output transistions
·Internal 75kΩ input pull-down resistors
·Available in 8-pin SOIC package

简介

SY100EL33属于集成电路（IC）的计数器除法器。由制造生产的SY100EL33计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。