SY100EL15L集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

DESCRIPTION

The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current.

FEATURES

■ 3.3V power supply

■ 50ps output-to-output skew

■ Low power

■ Synchronous enable/disable

■ Multiplexed clock input

■ 75KΩ internal input pull-down resistors

■ Available in 16-pin SOIC package