SY100E150JC集成电路（IC）的锁存器规格书PDF中文资料

DESCRIPTION

The SY10/100E150 are 6-bit D latches with differential outputs designed for use in new, high- performance ECL systems. When both Latch Enables (LEN1, LEN2) are at a logic LOW, the latch is in the transparent mode and input data propagates through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the input data. The Master Reset (MR) overrides all other signals to set the Q outputs to a logic LOW.

FEATURES

■ 700ps max. propagation delay

■ Extended 100E VEE range of –4.2V to –5.5V

■ Differential outputs

■ Fully compatible with industry standard 10KH, 100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E150

■ Available in 28-pin PLCC package