SY100E111JCTR中文资料麦瑞半导体数据手册PDF规格书

DESCRIPTION

The SY10/100E111 are low skew 1-to-9 differential drivers designed for clock distribution in new, high performance ECL systems. They accept one differential or single-ended input, with VBB used for single-ended operation. The signal is fanned out to nine identical differential outputs. An enable input is also provided such that a logic HIGH disables the device by forcing all Q outputs LOW and all /Q outputs HIGH.

FEATURES

■ Low skew

■ Extended 100E VEE range of –4.2V to –5.5V

■ Guaranteed skew limits

■ Differential design

■ VBB output

■ Enable input

■ Fully compatible with industry standard 10KH, 100K I/O levels

■ 75KΩ input pulldown resistors

■ Fully compatible with ON Semiconductor MC10E/100E111

■ Available in 28-pin PLCC package