STR750FV0数据手册ST中文资料规格书

特性 Features

• 8 Communications interfaces1 I2C interface3 HiSpeed UARTs w. Modem/LIN capability2 SSP interfaces (SPI or SSI) up to 16 Mb/s1 CAN interface (2.0B Active)1 USB full-speed 12 Mb/s interface with 8 configurable endpoint sizes
• 6 Timers16-bit watchdog timer (WDG)16-bit timer for system timebase functions3 synchronizable timers each with up to 2 input captures and 2 output compare/PWMs.16-bit 6-ch. synchronizable PWM timerDead time generation, edge/center-aligned waveforms and emergency stopIdeal for induction/brushless DC motors
• Up to 72/38 I/O ports72/38 GPIOs with High Sink capabilitiesAtomic bit SET and RES operations
• CoreARM7TDMI-S 32-bit RISC CPU54 DMIPS @ 60 MHz
• Clock, reset and supply managementSingle supply 3.3V ±10% or 5V ±10%Embedded 1.8V Voltage RegulatorsInt. RC for fast start-up and backup clockUp to 60 MHz operation using internal PLL with 4 or 8 MHz crystal/ceramic osc.Smart Low Power Modes: SLOW, WFI, STOP and STANDBY with backup registersReal-time Clock, driven by low power internal RC or 32.768 kHz dedicated osc, for clock-calendar and Auto Wake-up
• MemoriesUp to 256 KB Flash program memory (10k W/E cycles, retention 20 yrs @ 85°C)16 KB Read-While-Write Flash for data (100k W/E cycles, retention 20 yrs@ 85°C)Flash Data Readout and Write Protection16KBytes embedded high speed SRAMMemory mapped interface (SMI) to ext. Serial Flash (64 MB) w. boot capability
• DMA4-channel DMA controllerCircular buffer managementSupport for UART, SSP, Timers, ADC
• 10-bit A/D converter16/11 chan. with prog. Scan Mode & FIFOProgrammable Analog Watchdog featureConversion time: min. 3.75 μsStart conversion can be triggered by timers
• Nested interrupt controllerFast interrupt handling with 32 vectors16 IRQ priorities, 2 maskable FIQ sources16 external interrupt / wake-up lines