STM8S103F3M3TR中文资料意法半导体数据手册PDF规格书

Description

The STM8S103/105 access line 8-bit microcontrollers offer from 8 Kbytes up to 32 Kbytes of program memory.

All devices of the STM8S103/105 access line provide the following benefits:

● Reduced system cost

– High system integration level with internal clock oscillators, watchdog and brown out reset

● Performance and robustness

– 16 MHz CPU clock frequency

– Robust I/O, independent watchdogs with separate clock source

– Clock security system

● Short development cycles

– Applications scalability across a common family product architecture with compatible pinout, memory map and and modular peripherals.

– Full documentation and a wide choice of development tools

● Product longevity

– Advanced core and peripherals made in a state-of-the art technology

– A family of products for applications with 3.0 V to 5.5 V operating supply

Features

Core

■ Max fCPU: up to 16 MHz

■ Advanced STM8 core with Harvard architecture and 3-stage pipeline

■ Extended instruction set

Memories

■ Program memory: Up to 32 Kbytes Flash; data retention 20 years at 85°C after 1 kcycles

■ RAM: Up to 2 Kbytes

Clock, reset and supply management

■ 3.0 to 5.5 V operating voltage

■ Flexible clock control, 4 master clock sources:

– Low power crystal resonator oscillator

– External clock input

– Internal 16 MHz RC

– Internal low power 128 kHz RC

■ Clock security system with clock monitor

■ Power management:

– Low power modes (Wait, Active-halt, Halt)

– Switch-off peripheral clocks individually

■ Permanently active, low consumption power on and power-down reset

Interrupt management

■ Nested interrupt controller with 32 interrupts

■ Up to 37 external interrupts on 6 vectors

Timers

■ 2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM)

■ Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

■ 8-bit basic timer with 8-bit prescaler

■ Auto wake-up timer

■ 2 watchdog timers: Window watchdog and independent watchdog

Communications interfaces

■ USART or LINUART with clock output for synchronous operation, smartcard mode, IrDA mode, LIN master mode

■ SPI synchronous serial interface up to 8 Mbit/s

■ I2C interface up to 400 Kbit/s

Analog to digital converter (ADC)

■ 10-bit, ±1 LSB ADC with up to 10 multiplexed channels, scan mode and analog watchdog

I/Os

■ Up to 38 I/Os on a 48-pin package including 9 high sink outputs

■ Highly robust I/O design, immune against current injection