Automotive 8-bit MCU, with up to 128-Kbyte Flash memory, data EEPROM, 10-bit ADC, timers, LIN, USART, SPI, I2C, 3 to 5.5 V

Features • AEC-Q10x qualified • Core – Max fCPU: 24 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline – Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark • Memories – Program memory: 32 to 128 Kbyte Flash program; d

文件：2.01184 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体

Automotive 8-bit MCU, with up to 128-Kbyte Flash memory, data EEPROM, 10-bit ADC, timers, LIN, USART, SPI, I2C, 3 to 5.5 V

Features • AEC-Q10x qualified • Core – Max fCPU: 24 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline – Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark • Memories – Program memory: 32 to 128 Kbyte Flash program; d

文件：2.01184 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体

Automotive 8-bit MCU, with up to 128-Kbyte Flash memory, data EEPROM, 10-bit ADC, timers, LIN, USART, SPI, I2C, 3 to 5.5 V

Features • AEC-Q10x qualified • Core – Max fCPU: 24 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline – Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark • Memories – Program memory: 32 to 128 Kbyte Flash program; d

文件：2.01184 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体

Automotive 8-bit MCU, with up to 128-Kbyte Flash memory, data EEPROM, 10-bit ADC, timers, LIN, USART, SPI, I2C, 3 to 5.5 V

Features • AEC-Q10x qualified • Core – Max fCPU: 24 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline – Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark • Memories – Program memory: 32 to 128 Kbyte Flash program; d

文件：2.01184 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体

Automotive 8-bit MCU, with up to 128-Kbyte Flash memory, data EEPROM, 10-bit ADC, timers, LIN, USART, SPI, I2C, 3 to 5.5 V

Features • AEC-Q10x qualified • Core – Max fCPU: 24 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline – Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark • Memories – Program memory: 32 to 128 Kbyte Flash program; d

文件：2.01184 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体