Automotive 8-bit MCU, with up to 32 Kbyte Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5 V

Features • AEC-Q10x qualified • Core – Max fCPU: 16 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline – Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark • Memories – Flash Program memory: 16 to 32 Kbyte Flash; data ret

文件：1.37598 Mbytes 页数：99 Pages

STMICROELECTRONICS

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Automotive 8-bit MCU, with up to 32 Kbyte Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5 V

Features • AEC-Q10x qualified • Core – Max fCPU: 16 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline – Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark • Memories – Flash Program memory: 16 to 32 Kbyte Flash; data ret

文件：1.37598 Mbytes 页数：99 Pages

STMICROELECTRONICS

意法半导体

Automotive 8-bit MCU, with up to 32 Kbytes Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5 V

Introduction This datasheet refers to the STM8AF61xx (STM8AF612x, STM8AF614x, STM8AF6166, and STM8AF6168) and STM8AF62xx products with 16 to 32 Kbytes of Flash program memory. In the order code, the letter ‘F’ refers to product versions with data EEPROM and ‘H’ refers to product versions without

文件：1.3626 Mbytes 页数：89 Pages

STMICROELECTRONICS

意法半导体

Automotive 8-bit MCU, with up to 32 Kbyte Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5 V

Features • AEC-Q10x qualified • Core – Max fCPU: 16 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline – Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark • Memories – Flash Program memory: 16 to 32 Kbyte Flash; data ret

文件：1.37598 Mbytes 页数：99 Pages

STMICROELECTRONICS

意法半导体

Automotive 8-bit MCU, with up to 32 Kbyte Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5 V

Features • AEC-Q10x qualified • Core – Max fCPU: 16 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline – Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark • Memories – Flash Program memory: 16 to 32 Kbyte Flash; data ret

文件：1.37598 Mbytes 页数：99 Pages

STMICROELECTRONICS

意法半导体