STM32U5G9VJ中文资料意法半导体数据手册PDF规格书

特性 Features

Includes ST state-of-the-art patented

technology

Ultra-low-power with FlexPowerControl

• 1.71 V to 3.6 V power supply

• - 40 °C to + 85°C temperature range

• LPBAM: autonomous peripherals with DMA,

functional down to Stop 2 mode

• VBAT mode: supply for RTC, 32 x 32-bit backup

registers and 2-Kbyte backup SRAM

• 150 nA Shutdown mode (24 wake-up pins)

• 195 nA Standby mode (24 wake-up pins)

• 480 nA Standby mode with RTC

• 2.05 μA Stop 3 mode with 40-Kbyte SRAM

• 8.25 μA Stop 3 mode with 3-Mbyte SRAM

• 4.05 μA Stop 2 mode with 40-Kbyte SRAM

• 15.5 μA Stop 2 mode with 3-Mbyte SRAM

• 18.6 μA/MHz Run mode at 3.3 V

Core

• Arm® 32-bit Cortex®-M33 CPU with

TrustZone®, MPU, DSP, and FPU

ART Accelerator

• 32-Kbyte ICACHE allowing 0-wait-state

execution from flash and external memories:

frequency up to 160 MHz, 240 DMIPS

• 16-Kbyte data cache for external memories

Power management

• Embedded regulator (LDO) and SMPS

step-down converter supporting switch

on-the-fly and voltage scaling

Performance benchmark

• 1.5 DMIPS/MHz (Drystone 2.1)

• 655 CoreMark® (4.09 CoreMark®/MHz)

Memories

• 4-Mbyte flash memory with ECC, 2 banks

read-while-write, including 512 Kbytes with

100 kcycles

• With SRAM3 ECC off: 3026-Kbyte RAM

including 66 Kbytes with ECC

• With SRAM3 ECC on: 2962-Kbyte RAM

including 322 Kbytes with ECC

• External memory interface supporting SRAM,

PSRAM, NOR, NAND and FRAM memories

• 2 Octo-SPI memory interfaces

• HSPI memory interface up to 160 MHz

Rich graphic features

• Neo-Chrom VG processor (GPU2D)

accelerating any angle rotation, scaling and

perspective correct texture mapping, and

vector graphics

• Chrom-ART Accelerator (DMA2D) for

enhanced graphic content creation

• Chrom-GRC (GFXMMU) allowing up to 20 %

of graphic resources optimization

• MIPI® DSI Host controller with two DSI lanes

running at up to 500 Mbit/s each

• LCD-TFT controller (LTDC)

• Digital camera interface

• Hardware JPEG codec

• Dedicated graphic timer

General-purpose input/outputs

• Up to 151 fast I/Os with interrupt capability

most 5V-tolerant and up to 14 I/Os with

independent supply down to 1.08 V

Clock management

• 4 to 50 MHz crystal oscillator

• 32 kHz crystal oscillator for RTC (LSE)

• Internal 16 MHz factory-trimmed RC (± 1 %)

• Internal low-power 32 kHz RC (± 5 %)

• 2 internal multispeed 100 kHz to 48 MHz

oscillators, including one auto-trimmed by LSE

• Internal 48 MHz

• 3 PLLs for system clock, USB, audio, ADC

Security and cryptography

• SESIP3 and PSA Level 3 Certified Assurance

Target

• Arm® TrustZone® and securable I/Os,

memories and peripherals

• Flexible life-cycle scheme with RDP and

password-protected debug

• Root of trust thanks to unique boot entry and

secure hide-protection area (HDP)

• SFI (secure firmware installation) thanks to

embedded RSS (root secure services)

• Secure data storage with hardware unique

key (HUK)

• Secure firmware upgrade support with TF-M

• 2 AES coprocessors including one with DPA

resistance

• Public key accelerator, DPA resistant

• On-the-fly decryption of Octo-SPI external

memories

• HASH hardware accelerator

• True random number generator, NIST

SP800-90B compliant

• 96-bit unique ID

• 512-byte OTP (one-time programmable)

• Active tampers

Up to 17 timers, 2 watchdogs and RTC

• 19 timers: 2 16-bit advanced motor-control,

4 32-bit, 3 16-bit general purpose, 2 16-bit

basic, 4 low-power 16-bit (available in Stop

mode), 2 SysTick timers, and 2 watchdogs

• RTC with calendar, alarms, and calibration

Up to 25 communication peripherals

• 1 USB Type-C®/USB Power Delivery controller

• 1 USB OTG high-speed with embedded PHY

• 2 SAIs (serial-audio interface)

• 6 I2C FM+(1 Mbit/s), SMBus/PMBus®

• 7 USARTs (ISO 7816, LIN, IrDA, modem)

• 3 SPIs (5x SPIs with the dual OCTOSPI)

• 1 CAN FD controller

• 2 SDMMC interfaces

• 1 multifunction digital filter (6 filters) + 1 audio

digital filter with sound-activity detection

• Parallel synchronous slave interface

16- and 4-channel DMA controllers,

functional in Stop mode

Mathematical coprocessor

• CORDIC for trigonometric functions

acceleration and FMAC

Up to 24 capacitive sensing channels

Rich analog peripherals (independent

supply)

• 2 × 14-bit ADC 2.5-Msps with hardware

oversampling

• 1 × 12-bit ADC 2.5-Msps, with hardware

oversampling, autonomous in Stop 2 mode

• 12-bit DAC (2 channels), low-power sample

and hold, autonomous in Stop 2 mode

• 2 operational amplifiers with built-in PGA

• 2 ultra-low-power comparators

CRC calculation unit

Debug

• Development support: serial-wire debug

(SWD), JTAG, ETM

ECOPACK2 compliant packages

Table 1. Device summary