STM32MP255C中文资料意法半导体数据手册PDF规格书

Features

Includes ST state-of-the-art patented technology.

Cores

• Up to 64-bit dual-core Arm® Cortex®-A35

– Up to 1.5 GHz

– 32-Kbyte I + 32-Kbyte D level 1 cache for each core

– 512-Kbyte unified level 2 cache

– Arm® NEON™ and Arm® TrustZone®

• 32-bit Arm® Cortex®-M33 with FPU/MPU

– Up to 400 MHz

– L1 16-Kbyte I / 16-Kbyte D

– Arm® TrustZone®

• 32-bit Arm® Cortex®-M0+ in SmartRun domain

– Up to 200 MHz (up to 16 MHz in autonomous mode)

Memories

• External DDR memory up to 4 Gbytes

– Up to DDR3L-2133 16/32-bit

– Up to DDR4-2400 16/32-bit

– Up to LPDDR4-2400 16/32-bit

• 808-Kbyte internal SRAM: 256-Kbyte AXI SYSRAM, 128-Kbyte AXI video RAM

or SYSRAM extension, 256-Kbyte AHB SRAM, 128-Kbyte AHB SRAM with

ECC in backup domain, 8-Kbyte SRAM with ECC in backup domain, 32 Kbytes

in SmartRun domain

• Two Octo-SPI memory interfaces

• Flexible external memory controller with up to 16-bit data bus: parallel interface

to connect external ICs, and SLC NAND memories with up to 8-bit ECC

Security/safety

• Secure boot, TrustZone® peripherals, active tamper, environmental monitors,

display secure layers, hardware accelerators

• Complete resource isolation framework

Reset and power management

• 1.71 to 1.95 V and 2.7/3.0 to 3.6 V multiple section I/O supply

• POR, PDR, PVD, and BOR

• On-chip LDO and power-switches for RETRAM, BKPSRAM, VSW, and

SmartRun domains

• Dedicated supplies for Cortex®-A35 and GPU/NPU (if present)

• Internal temperature sensors

• Low-power modes: Sleep, Stop, and Standby

• DDR memory retention in Standby mode

• Controls for PMIC companion chip

Low-power consumption

Clock management

• Internal oscillators: 64 MHz HSI, 4/16 MHz MSI, 32 kHz LSI

• External oscillators: 16-48 MHz HSE, 32.768 kHz LSE

• Up to 8× PLLs with fractional mode

General-purpose inputs/outputs

• Up to 172 secure I/O ports with interrupt capability

– Up to 6 wake-up inputs

– Up to 8 tamper input pins + 8 active tampers output pins

Interconnect matrix

• Bus matrices

– 128-, 64-, 32-bit STNoC interconnect, up to 600 MHz

– 32-bit Arm® AMBA® AHB interconnect, up to 400 MHz

4 DMA controllers to unload the CPU

• 48 + 4 physical channels in total

• 3× dual master port, high-performance, general-purpose, direct memory access controller (HPDMA), 16

channels each

• 1× low-power DMA controller with 4 channels in SmartRun domain

Up to 51 communication peripherals

• 8× I2C FM+ (1 Mbit/s, SMBus/PMBus®)

• 4× I3C (12.5 Mbit/s)

• 5× UART + 4× USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI) + 1× LPUART

• 8× SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy via internal audio PLL or external

clock)(+2 with OCTOSPI + 4 with USART)

• 4× SAI (stereo audio: I2S, PDM, SPDIF Tx)

• SPDIF Rx with 4 inputs

• 3× SDMMC up to 8-bit (SD/e•MMC™/SDIO)

• Up to 3× CAN controllers supporting CAN FD protocol, out of which one supports time-triggered CAN

(TTCAN)

• 1× USB 2.0 high-speed Host with embedded 480 Mbits/s PHY

• 1× USB 2.0/3.0 high-speed/SuperSpeed dual role data with embedded 480 Mbits/s and 5 Gbits/s PHY

(5 Gbits/s PHY shared with PCI Express)

• 1× USB Type-C® Power Delivery control with two CC lines PHY

• 1 × PCI Express with embedded 5 Gbits/s PHY (PHY shared with USB 3.0 SuperSpeed)

• Up to 3× Gigabit Ethernet interfaces

– 1× Gigabit Ethernet GMAC with one PHY interface (optional)

– 1× Gigabit Ethernet GMAC with one external PHY interface, optionally internally connected to one

embedded Ethernet switch providing two external PHY interfaces

– TSN, IEEE 1588v2 hardware, MII/RMII/RGMII

• Camera interface #1 (5 Mpixels @30 fps)

– MIPI CSI-2®, 2× data lanes up to 2.5 Gbit/s each

– 8- to 16-bit parallel, up to 120 MHz

– RGB, YUV, JPG, RawBayer with Lite-ISP

– Lite-ISP, demosaicing, downscaling, cropping, 3 pixel pipelines

• Camera interface #2 (1 Mpixels @15 fps)

– 8- to 14-bit parallel, up to 80 MHz

– RGB, YUV, JPG

– Cropping

• Digital parallel interface up to 16-bit input or output

7 analog peripherals

• 3 × ADCs with 12-bit max. resolution (up to 5 Msps each, up to 23 channels)

• Internal temperature sensor (DTS)

• 1× multifunction digital filter (MDF) with up to 8 channels/8 filters

• 1× audio digital filter (ADF) with 1 filter and sound activity detection

• Internal (VREFBUF) or external ADC reference VREF+

Graphics

• Optional 3D GPU: VeriSilicon® - Up to 900 MHz

– OpenGL® ES 3.1 - Vulkan 1.3

– OpenCL™ 3.0, OpenVX™ 1.3

– Up to 150 Mtriangle/s, 900 Mpixel/s

• LCD-TFT controller, up to 24-bit // RGB888

– Up to FHD (1920 × 1080) @60 fps

– 3 layers including a secure layer

– YUV support, 90° output rotation

• Optional MIPI DSI®, 4× data lanes, up to 2.5 Gbit/s each

– Up to QXGA (2048 × 1536) @60 fps

• Optional FPD-1 and OpenLDI JEIDA/VESA (LVDS), up to 2× links of 4× data lanes, up to 1.1 Gbit/s per

lane

– Up to QXGA (2048 × 1536) @60 fps

Artificial intelligence

• Optional NPU: VeriSilicon® - Up to 900 MHz

– TensorFlowLite - ONNX - Linux NN

Video processing

• Optional hardware video encoder and decoder up to 600 MHz

– H264/VP8 up to FHD (1920×1080) @60 fps

– JPEG up to 500 Mpixel/s

– 128 Kbytes of video RAM

Up to 34 timers and 7 watchdogs

• 4× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

• 3× 16-bit advanced motor control timers

• 10× 16-bit general-purpose timers (including 2 basic timers without PWM)

• 5× 16-bit low-power timers

• Secure RTC with subsecond accuracy and hardware calendar

• Up to 2× 4 Cortex®-A35 system timers (secure, non-secure, virtual, hypervisor)

• 2× SysTick Cortex®-M33 timer (secure, non-secure)

• 1× SysTick Cortex®-M0+ timer

• 7× watchdogs (5× independent and 2× window)

Hardware acceleration

• AES-128, -192, -256, DES/TDES

• Secure AES-256 with SCA

• RSA, ECC, ECDSA with SCA

• HASH (SHA-1, SHA-224, SHA-256, SHA3), HMAC

• True random number generator

• CRC calculation unit

• “On-the-fly” DDR encryption/decryption (AES-128)

• “On-the-fly” OTFDEC Octo-SPI flash memory decryption (AES-128)

Debug mode

• Arm® CoreSight™ trace and debug: SWD and JTAG interfaces

12288-bit fuses including 96-bit unique ID

All packages are ECOPACK2 compliant