STM32H563ZG中文资料意法半导体数据手册PDF规格书

Features

Includes ST state-of-the-art patented

technology

Core

• Arm® Cortex®-M33 CPU with TrustZone®,

FPU, frequency up to 250 MHz, MPU,

375 DMIPS (Dhrystone 2.1)

ART Accelerator

• 8-Kbyte instruction cache allowing

0-wait-state execution from flash and external

memories

• 4-Kbyte data cache for external memories

Benchmarks

• 1.5 DMIPS/MHz (Drystone 2.1)

• 1023 CoreMark® (4.092 CoreMark®/MHz)

Memories

• Up to 2 Mbytes of embedded flash memory

with ECC, two banks read-while-write

• Up to 48-Kbyte per bank with high-cycling

capability (100 K cycles) for data flash

• 2-Kbyte OTP (one-time programmable)

• 640 Kbytes of SRAM (64-Kbyte SRAM2 with

ECC and 320-Kbyte SRAM3 with flexible ECC)

• 4 Kbytes of backup SRAM available in the

lowest power modes

• Flexible external memory controller with up to

16-bit data bus: SRAM, PSRAM, FRAM,

SDRAM/LPSDR SDRAM, NOR/NAND

memories

• One Octo-SPI memory interface with support

for serial PSRAM/NAND/NOR, hyper

RAM/flash frame formats

• Two SD/SDIO/MMC interfaces

Clock management

• Internal oscillators: 64 MHz HSI,

48 MHz HSI48, 4 MHz CSI, 32 kHz LSI

• External oscillators: 4-50 MHz HSE,

32.768 kHz LSE

General-purpose inputs/outputs

• Up to 140 fast I/Os with interrupt capability

(most of them 5 V-tolerant)

• Up to ten I/Os with independent supply down to

1.08 V

Low-power consumption

• Sleep, Stop, and Standby modes

• VBAT supply for RTC, 32 backup registers

(32-bit)

Security

• Arm® TrustZone® with Armv8-M mainline

security extension

• Up to eight configurable SAU regions

• TrustZone® aware and securable peripherals

• Flexible life cycle scheme with secure debug

authentication

• SFI (secure firmware installation)

• Secure firmware upgrade support with TF-M

• HASH hardware accelerator

• ECDSA signature verification

• True random number generator, NIST

SP800-90B compliant

• 96-bit unique ID

• Active tampers

Two DMA controllers to offload the CPU

• Two dual-port DMAs with FIFO

Mathematical acceleration

• CORDIC for trigonometric functions

acceleration

• FMAC (filter mathematical accelerator)

Reset and supply management

• 1.71 V to 3.6 V application supply and I/O

• POR, PDR, PVD, and BOR

• Embedded regulator (LDO) or SMPS stepdown

converter regulator with configurable

scalable output to supply the digital circuitry

Up to 24 timers

• 18 16-bit timers (including six low-power

16-bit timers available in Stop mode)

• Two 32-bit timers with up to four IC/OC/PWM

or pulse counters and quadrature (incremental)

encoder input

• Two watchdogs

• Two SysTick timers

Up to 34 communication interfaces

• Up to four I2Cs Fm+ (SMBus/PMBus®)

• One I3C

• Up to 12 U(S)ARTs (ISO7816 interface, LIN,

IrDA, modem control) and one LPUART

• Up to six SPIs, including three muxed in

full-duplex I2S audio class accuracy via

internal audio PLL or external clock, and up to

five additional SPIs from five USARTs when

configured in Synchronous mode (one

additional SPI with OctoSPI)

• Two SAIs

• Two FDCANs

• One 8- to 14-bit camera interface

• One 16-bit parallel slave synchronousinterface

• One HDMI-CEC

• One Ethernet MAC interface with DMA

controller

• One USB 2.0 full-speed host and device

• One USB Type-C®/USB Power Delivery r3.1

Analog

• Two 12-bit ADCs with up to 5 Msps in 12-bit

• One 12-bit DAC with two channels

• Digital temperature sensor

Debug

• Authenticated debug and flexible device life

cycle

• Serial wire-debug (SWD), JTAG, Embedded

Trace Macrocell™ (ETM)

ECOPACK2 compliant packages