Medium-density performance line Arm®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Features  Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS / MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM  Clock, reset and sup

文件：2.03321 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces

文件：1.21833 Mbytes 页数：92 Pages

STMICROELECTRONICS

意法半导体

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces

文件：1.43691 Mbytes 页数：96 Pages

STMICROELECTRONICS

意法半导体

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

The STM32F103xx medium-density performance line family incorporates the high performance ARM Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, high speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 20 Kbytes), and an extensive range of enhanced I/Os and peripherals

文件：1.31619 Mbytes 页数：105 Pages

STMICROELECTRONICS

意法半导体

Medium-density performance line Arm®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Features  Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS / MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM  Clock, reset and sup

文件：2.03321 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces

文件：1.21833 Mbytes 页数：92 Pages

STMICROELECTRONICS

意法半导体