Leading-edge architecture with Cortex-M3 core

■ Harvard architecture ■ 1.25 DMIPS/MHz and 0.19 mW/MHz ■ Thumb-2 instruction set brings 32-bit performance with 16-bit code density ■ Single cycle multiply and hardware division ■ Embedded, fast interrupt controller is now inside the core allowing: ■ Excellent real-time behaviour ■ Low la

文件：140.5 Kbytes 页数：6 Pages

STMICROELECTRONICS

意法半导体

Leading-edge architecture with Cortex-M3 core

■ Harvard architecture ■ 1.25 DMIPS/MHz and 0.19 mW/MHz ■ Thumb-2 instruction set brings 32-bit performance with 16-bit code density ■ Single cycle multiply and hardware division ■ Embedded, fast interrupt controller is now inside the core allowing: ■ Excellent real-time behaviour ■ Low la

文件：140.5 Kbytes 页数：6 Pages

STMICROELECTRONICS

意法半导体

Leading-edge architecture with Cortex-M3 core

■ Harvard architecture ■ 1.25 DMIPS/MHz and 0.19 mW/MHz ■ Thumb-2 instruction set brings 32-bit performance with 16-bit code density ■ Single cycle multiply and hardware division ■ Embedded, fast interrupt controller is now inside the core allowing: ■ Excellent real-time behaviour ■ Low la

文件：140.5 Kbytes 页数：6 Pages

STMICROELECTRONICS

意法半导体

Leading-edge architecture with Cortex-M3 core

■ Harvard architecture ■ 1.25 DMIPS/MHz and 0.19 mW/MHz ■ Thumb-2 instruction set brings 32-bit performance with 16-bit code density ■ Single cycle multiply and hardware division ■ Embedded, fast interrupt controller is now inside the core allowing: ■ Excellent real-time behaviour ■ Low la

文件：140.5 Kbytes 页数：6 Pages

STMICROELECTRONICS

意法半导体