STLVD112中文资料意法半导体数据手册PDF规格书

DESCRIPTION

The STLVD112 is a low voltage differential to LVTTL signal converter with enhanced loop-back and crosspoint features. The synchronous design allows a phase alignment between a clock and its data; this means a better BER (Bit Error Rate) performance.

The advanced 0.35µm technology makes the STLVD112 suitable for data rates up to 200Mbit. The main application field is SDH/SONET telecom infrastructure. The STLVD112 flexible switch architecture makes it easy to implement multiple protection schemes in STM1 access systems.

■ 24mA CMOS OUTPUT DRIVE CURRENT

■ LVTTL INPUT THRESHOLDS

■ CONTROLLED SKEW BETWEEN DATA AND CLOCK SIGNALS

■ LVDS INPUT-OUTPUT UP TO 155 MHZ

■ IMPROVED LATCH-UP IMMUNITY UP TO 300mA