STA5635S数据手册ST中文资料规格书

描述 Description

The STA5635S is a fully integrated RF front-end able to support different bands (L1/E1, L2C, L5/E5/E6) thanks to a programmable and flexible RF-IF chain driven by a fractional PLL. In particular, STA5635S is able to manage all the GNSS constellations available and planned in the next future like GPS, Galileo, Glonass, BeiDou, IRNSS and QZSS.
The RF_IF chain is followed from a 2-bit ADC able to convert the IF signal to Sign (SIGN) and Magnitude (MAG) bit. The MAG bit is internally integrated in order to control the variable gain amplifiers. The VGA gain can be also set by the SPI interface.
The embedded fractional PLL allows supporting a wide range of reference clocks (10 to 55 MHz) and generates a sampling clock available for the baseband.
The STA5635S embeds two LDOs to supply at 1.1 V the analog and digital cores of the device facilitating requirements to external power supply. A third LDO can be turned-on to supply at 1.8 V external active components as a TCXO.
The chip is manufactured in CMOS040nm technology and housed in a QFN package.

特性 Features

• AEC-Q100 Grade 2
• Multi GNSS band support (L1/E1, L2C, L5/E5/E6)
• Programmable IF bandwidth (7 or 13 MHz range)
• 3.3 V supply voltage
• Fractional-N synthesizer with embedded loop filter
• SPI Interface for full programmability
• 2 Bit A/D converter
• ASIL compliance
• Operating temperature (-40, +105 °C)
• CMOS040 technology
• QFN5x5 32 leads package