ST6200C中文资料意法半导体数据手册PDF规格书

INTRODUCTION

The ST6200C, 01C and 03C devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a common core is surrounded by a number of on-chip peripherals.

The ST62E01C is the erasable EPROM version of the ST62T00C, T01 and T03C devices, which may be used during the development phase for the ST62T00C, T01 and T03C target devices, as well as the respective ST6200C, 01C and 03C ROM devices.

■ Memories

– 1K or 2K bytes Program memory (OTP,

EPROM, FASTROM or ROM) with read-out

protection

– 64 bytes RAM

■ Clock, Reset and Supply Management

– Enhanced reset system

– Low Voltage Detector (LVD) for Safe Reset

– Clock sources: crystal/ceramic resonator or

RC network, external clock, backup oscillator

(LFAO)

– Oscillator Safeguard (OSG)

– 2 Power Saving Modes: Wait and Stop

■ Interrupt Management

– 4 interrupt vectors plus NMI and RESET

– 9 external interrupt lines (on 2 vectors)

■ 9 I/O Ports

– 9 multifunctional bidirectional I/O lines

– 4 alternate function lines

– 3 high sink outputs (20mA)

■ 2 Timers

– Configurable watchdog timer

– 8-bit timer/counter with a 7-bit prescaler

■ Analog Peripheral

– 8-bit ADC with 4 input channels (except on

ST6203C)

■ Instruction Set

– 8-bit data manipulation

– 40 basic instructions

– 9 addressing modes

– Bit manipulation

■ Development Tools

– Full hardware/software development package