ST33K512M数据手册ST中文资料规格书

描述 Description

The ST33K platform is a serial access microcontroller designed for secure machine-to-machine (M2M) applications in the industrial environment. It incorporates the most recent generation of Arm® processors for embedded secure systems. Its Cortex®-M35P 32-bit RISC core includes additional security features to help protect against advanced forms of attack.\r
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The ST33K platform provides high performance thanks to a fast Cortex®-M35P processor, cryptographic accelerators and improved flash memory operations.\r
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Cadenced at 63 MHz, the Cortex®-M35P core brings great performance and excellent code density thanks to the Thumb®-2 instruction set.\r
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Strong and multiple fault protection mechanisms ensure a guaranteed high-detection coverage that facilitates the development of highly secure software. This is achieved by using two CPUs in Lockstep mode, error detection in sensitive memories and hardware logic.\r
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The ST33K platform offers two serial communication slave interfaces fully compatible with the ISO/IEC 7816-3 standard (T=0, T=1) and a single-wire protocol (SWP) slave interface for communication with a near field communication (NFC) router in secure element (SE) applications. The device also includes a master/slave serial peripheral interface (SPI) as well as an inter-integrated circuit (I²C) master/slave interface for communication. The slave SPI runs at up to 48 MHz and the master SPI at up to 15 MHz while the slave I²C Fast-mode Plus interface operates at up to 1 Mbit/s and the master I²C Fast-mode plus at up to 1 Mbit/s.\r
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Three general-purpose 16-bit timers as well as a watchdog timer are available.\r
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One permanent timer (PMT) with a count capability in low-power mode is available.\r
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The ST33K platform features hardware accelerators for advanced cryptographic functions. The EDES+ peripheral provides a secure DES (data encryption standard) algorithm implementation, while the NESCRYPT LLP cryptoprocessor efficiently supports the public key algorithm. The AES (advanced encryption standard) and SM4 peripherals ensure secure and fast AES and SM4 algorithm implementations.\r
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The ST33K platform operates in the –40 to +105 °C temperature range and 1.8 V, 3 V and 3.3 V supply voltage ranges.\r
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In terms of application, STMicroelectronics offers the following optional software package: NesLib cryptographic library.\r
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In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

特性 Features

• Hardware features
•Arm® Cortex®-M35P 32-bit RISC core cadenced at 63 MHz
•Operating temperature range: –40 to +105 °C
•2 Kbytes of cache memory
•Up to 1.5 Mbytes of user flash memory
•64 Kbytes of user RAM
•External interfaces
• Two ISO/IEC 7816-3 interfaces supporting the T=0 and T=1 protocols (slave mode)
• Single-wire protocol (SWP) slave interface (ETSI 102613 compliant)
• Serial peripheral interface (SPI) - master (up to 15 MHz) and slave (up to 48 MHz)
• Master/slave I²C interface up to 1 Mb/s

•Three 16-bit timers with interrupt capability
•Permanent timer in low-power standby mode
•Watchdog timer
•Ten multiplexed general-purpose I/Os
•Class C (1.8 V), Class B (3 V) and 3.3 V supply voltage ranges
•Current consumption compatible with GSM and ETSI TS 102 221 release 12 and beyond
•Contact assignment compatible with ISO/IEC 7816-2
•ESD protection greater than 4 kV (HBM)
•Delivery forms:
• D16 micromodule
• WLCSP24 and wettable flank VFDFPN8 (5 × 6 mm) ECOPACK-compliant packages
• Sawn/unsawn 12” wafers

•JEDEC JESD47-compliant
•Machine-to-machine (M2M) ETSI TS 102 671 release 12 compliant (with TB/CA/RC/UB)
• Security features
•Platform and flash memory loader security certification target: Common Criteria
•Hardware security-enhanced DES accelerator
•Hardware security-enhanced AES accelerator
•Optional hardware security-enhanced SM4 accelerator
•NESCRYPT LLP coprocessor for public key cryptography algorithm
•16- and 32-bit CRC calculation block (such as ISO 13239 and IEEE 802.3)
•Active shield
•Highly efficient protection against faults
•True random number generator
• Software features
•Secure flash memory loader with high-speed downloading and post-delivery loading ability
•Optional security-certified cryptographic library \"NesLib\"