ST33K1M0C中文资料High-speed secure MCU with 32-bit Arm® Cortex®-M35P CPU数据手册ST规格书

描述 Description

所有功能Hardware featuresArm® Cortex®-M35P 32-bit RISC core cadenced at 70 MHzOperating temperature range: −30°C to 85 °C2 Kbytes of cache memory Up to 1.5 Mbytes of User Flash memory 64 Kbytes of User RAM External interfaces Two ISO/IEC 7816-3 interfaces supporting the T=0 and T=1 protocols (Slave mode)Single-wire protocol (SWP) slave interface (ETSI 102613 compliant)Serial peripheral interface (SPI) - Master (up to 17 MHz) and Slave (up to 48 MHz)Master/Slave I²C interface up to 1 Mb/sThree 16-bit timers with interrupt capability Permanent timer in low-power Standby mode Watchdog timer Ten multiplexed general-purpose I/Os Class C (1.8 V), Class B (3 V) and 3.3 V supply voltage ranges Current consumption compatible with GSM and ETSI TS 102 221 release 12 and beyond Contact assignment compatible with ISO/IEC 7816-2 ESD protection greater than 4 kV (HBM) Delivery forms: D18 micromoduleWLCSP24 and wettable flank VFDFPN8 (5 × 6 mm) ECOPACK-compliant packagesSawn/unsawn 12” wafersSecurity featuresPlatform and Flash memory loader security certification target according to Common Criteria EMVCo™ / MTPS (Mobile Trustable Public Service Platform) Hardware security-enhanced DES accelerator Hardware security-enhanced AES accelerator Optional hardware security-enhanced SM4 accelerator MIFARE Classic® cryptography hardware accelerator NESCRYPT LLP coprocessor for public key cryptography algorithm 16- and 32-bit CRC calculation block (ISO 13239, IEEE 802.3, etc.) Active shield Highly efficient protection against faults True random number generator Software featuresSecure Flash memory loader with high-speed downloading and post-delivery loading abilityOptional security-certified cryptographic library \"NesLib\"

特性 Features

• Hardware features
• Arm® Cortex®-M35P 32-bit RISC core cadenced at 70 MHz
• Operating temperature range: −30°C to 85 °C
• 2 Kbytes of cache memory
• Up to 1.5 Mbytes of User Flash memory
• 64 Kbytes of User RAM
• External interfaces
• Two ISO/IEC 7816-3 interfaces supporting the T=0 and T=1 protocols (Slave mode)
• Single-wire protocol (SWP) slave interface (ETSI 102613 compliant)
• Serial peripheral interface (SPI) - Master (up to 17 MHz) and Slave (up to 48 MHz)
• Master/Slave I²C interface up to 1 Mb/s
• Three 16-bit timers with interrupt capability
• Permanent timer in low-power Standby mode
• Watchdog timer
• Ten multiplexed general-purpose I/Os
• Class C (1.8 V), Class B (3 V) and 3.3 V supply voltage ranges
• Current consumption compatible with GSM and ETSI TS 102 221 release 12 and beyond
• Contact assignment compatible with ISO/IEC 7816-2
• ESD protection greater than 4 kV (HBM)
• Delivery forms:
• D18 micromodule
• WLCSP24 and wettable flank VFDFPN8 (5 × 6 mm) ECOPACK-compliant packages
• Sawn/unsawn 12” wafers

• Security features
• Platform and Flash memory loader security certification target according to Common Criteria EMVCo™ / MTPS (Mobile Trustable Public Service Platform)
• Hardware security-enhanced DES accelerator
• Hardware security-enhanced AES accelerator
• Optional hardware security-enhanced SM4 accelerator
• MIFARE Classic® cryptography hardware accelerator
• NESCRYPT LLP coprocessor for public key cryptography algorithm
• 16- and 32-bit CRC calculation block (ISO 13239, IEEE 802.3, etc.)
• Active shield
• Highly efficient protection against faults
• True random number generator
• Software features
• Secure Flash memory loader with high-speed downloading and post-delivery loading ability
• Optional security-certified cryptographic library \"NesLib\"