ST10F273M数据手册ST中文资料规格书

描述 Description

The ST10F273M device is a new derivative of the STMicroelectronics®ST10 family of 16-bit single-chip CMOS microcontrollers.
The ST10F273M combines high CPU performance (up to 20 million instructions per second) with high peripheral functionality and enhanced I/O capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL.
The ST10F273M is processed in 0.18mm CMOS technology. The MCU core and the logic is supplied with a 5V to 1.8V on-chip voltage regulator. The part is supplied with a single 5V supply and I/Os work at 5V.
The ST10F273M is an optimized version of the ST10F273E, upward compatible with the following set of differences:
Maximum CPU frequency is 40 MHz
A single bank of IFlash has been implemented but the programming interface has been kept compatible with the ST10F273E
Identification registers: the IDMEM register reflects the Flash type difference and allows to differentiate the two devices by software
Improved EMC behavior thanks to the introduction of an internal RC filter on the 5V for the ballast transistors
The clock to the X-Peripherals is gated: X-Peripheral not used will not get the clock in order to reduce the power consumption.

特性 Features

• High performance 16-bit CPU with DSP functions
• 50ns instruction cycle time at 40 MHz max CPU clock
• Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator
• Enhanced boolean bit manipulations
• Single-cycle context switching support
• Memory organization
• 512 Kbyte on-chip Flash memory single voltage with erase/program controller (full performance, 32-bit fetch)
• 100 K erasing/programming cycles
• Up to 16 Mbyte linear address space for code and data (5 Mbytes with CAN or I2C)
• 2 Kbyte on-chip internal RAM (IRAM)
• 34 Kbyte on-chip extension RAM (XRAM)
• Programmable external bus configuration and characteristics for different address ranges
• 5 programmable chip-select signals
• Hold-acknowledge bus arbitration support
• Interrupt
• 8-channel peripheral event controller for single cycle interrupt driven data transfer
• 16-priority-level interrupt system with 56 sources, sampling rate down to 25ns
• Timers
• 2 multifunctional general purpose timer units with 5 timers
• Two 16-channel capture / compare units
• 4-channel PWM unit + 4-channel XPWM
• 24-channel A/D converter
• 16-channel 10-bit, accuracy +/-2 LSB
• 8-channel 10-bit, accuracy +/-5 LSB
• 4.85μs Minimum conversion time
• Serial channels
• 2 synch. / asynch. serial channels
• 2 high-speed synchronous channels
• I2C standard interface
• 2 CAN 2.0B interfaces operating on 1 or 2 CAN buses (64 or 2x32 messages, C-CAN version)
• Fail-safe protection
• Programmable watchdog timer
• Oscillator watchdog
• On-chip bootstrap loader
• Clock generation
• On-chip PLL and 4 to 12 MHz oscillator
• Direct or prescaled clock input
• Real time clock and 32 kHz on-chip oscillator
• Up to 111 general purpose I/O lines
• Individually programmable as input, output or special function
• Programmable threshold (hysteresis)
• Idle, power down and standby modes
• Single voltage supply: 5 V ±10% (embedded regulator for 1.8 V core supply)
• Temperature range: -40°C to 125°C