Package：64-TFSOP（0.240"，6.10mm 宽）；包装：托盘 类别：集成电路（IC） 专用逻辑器件 描述：IC BUS DVR UNIV 13-26BIT 64TSSOP

Renesas Electronics America Inc

Package：64-TFSOP（0.240"，6.10mm 宽）；包装：托盘 类别：集成电路（IC） 专用逻辑器件 描述：IC BUS DVR UNIV 13-26BIT 64TSSOP

Renesas Electronics America Inc

2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM

DESCRIPTION The SSTV16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. All inputs are compatible with the JEDEC standard for SSTL_2 with VREF normally at 0.5*VDD, except the LVCMOS reset (RESET) input. All outputs are

文件：124.65 Kbytes 页数：14 Pages

PHI

飞利浦

2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM

DESCRIPTION The SSTV16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. All inputs are compatible with the JEDEC standard for SSTL_2 with VREF normally at 0.5*VDD, except the LVCMOS reset (RESET) input. All outputs are

文件：124.65 Kbytes 页数：14 Pages

PHI

飞利浦

Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset

General Description The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. The device has been designed to meet the JEDEC DDR module re

文件：168.95 Kbytes 页数：8 Pages

Fairchild

仙童半导体