1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity and programmable output for DDR2-800 RDIMMs

文件：586.41 Kbytes 页数：31 Pages

PHI

飞利浦

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity and programmable output for DDR2-800 RDIMMs

文件：586.41 Kbytes 页数：31 Pages

PHI

飞利浦

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity and programmable output for DDR2-800 RDIMMs

文件：586.41 Kbytes 页数：31 Pages

PHI

飞利浦

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity and programmable output for DDR2-800 RDIMMs

文件：586.41 Kbytes 页数：31 Pages

PHI

飞利浦

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer

Overview The SSTUP32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC standard for the SSTUA32866 and SSTUB32866 registered buffers. The register is configurable (using configurat Configurable register supporting DDR2 up to 667 MT/s or 800 MT/s Registered DIMM applications\nConfigurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode\nProgrammable for normal or high output drive\nControlled multi-impedance output drivers enable optimal signal integrity and speed\nProgrammable for 6;

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