1.8 V configurable registered buffer for DDR2-667 RDIMM applications

文件：112.22 Kbytes 页数：19 Pages

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1.8 V configurable registered buffer for DDR2-667 RDIMM applications

文件：124.96 Kbytes 页数：20 Pages

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1.8 V configurable registered buffer for DDR2-667 RDIMM applications

文件：124.96 Kbytes 页数：20 Pages

恩XP

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

文件：124.96 Kbytes 页数：20 Pages

恩XP

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

Overview The SSTUA32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed for 1.7 V to 2.0 V VDD operation.\nAll clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimize Configurable register supporting DDR2 Registered DIMM applications\nConfigurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode\nControlled output impedance drivers enable optimal signal integrity and speed\nExceeds SSTUA32864 JEDEC specification speed performance (1.8 ns max. single-bit switching propag;

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