SST39VF512-45-4C-B3H中文资料SST数据手册PDF规格书

PRODUCT DESCRIPTION

The SST39LF512, SST39LF010,SST39LF020, SST39LF040 and SST39VF512, SST39VF010,SST39VF020, SST39VF040 are 64K x8, 128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF512/010/020/040 devices write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF512/010/020/040 devices write with a 2.7-3.6V power supply. The devices conform to JEDEC standard pinouts for x8 memories.

FEATURES:

• Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8

• Single Voltage Read and Write Operations

– 3.0-3.6V for SST39LF512/010/020/040

– 2.7-3.6V for SST39VF512/010/020/040

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption(typical values at 14 MHz)

– Active Current: 5 mA (typical)

– Standby Current: 1 µA (typical)

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Fast Read Access Time:

– 45 ns for SST39LF512/010/020/040

– 55 ns for SST39LF020/040

– 70 ns for SST39VF512/010/020/040

• Latched Address and Data

• Fast Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time:

1 second (typical) for SST39LF/VF512

2 seconds (typical) for SST39LF/VF010

4 seconds (typical) for SST39LF/VF020

8 seconds (typical) for SST39LF/VF040

• Automatic Write Timing

– Internal VPPGeneration

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

– 48-ball TFBGA (6mm x 8mm)

– 34-ball WFBGA (4mm x 6mm) for 1M and 2M

• All devices are RoHS compliant