SST34HF1681-70-4E-L1P中文资料SST数据手册PDF规格书

PRODUCT DESCRIPTION

The SST34HF1681 ComboMemory devices integrate a 1M x16 CMOS flash memory bank with a 512K x16 CMOS SRAM memory bank in a Multi-Chip Package (MCP). These devices are fabricated using SST’s proprietary, highperformance CMOS SuperFlash technology incorporating the split-gate cell design and thick oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF1681 devices are ideal for applications such as cellular phones, GPSs, PDAs and other portable electronic devices in a low power and small form factor system.

FEATURES:

• Flash Organization: 1M x16

• Dual-Bank Architecture for Concurrent Read/Write Operation

– 16 Mbit: 12 Mbit + 4 Mbit

• SRAM Organization:

– 8 Mbit: 512K x16

• Single 2.7-3.3V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 25 mA (typical)

– Standby Current: 20 µA (typical)

• Hardware Sector Protection (WP#)

– Protects 4 outer most sectors (4 KWord) in the larger bank by holding WP# low and unprotects by holding WP# high

• Hardware Reset Pin (RST#)

– Resets the internal state machine to reading data array

• Sector-Erase Capability

– Uniform 1 KWord sectors

• Block-Erase Capability

– Uniform 32 KWord blocks

• Read Access Time

– Flash: 70 and 90 ns

– SRAM: 70 and 90 ns

• Latched Address and Data

• Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Word-Program Time: 14 µs (typical)

– Chip Rewrite Time: 8 seconds (typical)

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

– Ready/Busy# pin

• CMOS I/O Compatibility

• JEDEC Standard Command Set

• Conforms to Common Flash Memory Interface (CFI)

• Packages Available

– 56-ball LFBGA (8mm x 10mm)