SST32HF1641C中文资料SST数据手册PDF规格书

PRODUCT DESCRIPTION

The SST32HFx1/x1C ComboMemory devices integrate a CMOS flash memory bank with a CMOS SRAM memory bank in a Multi-Chip Package (MCP), manufactured with SST’s proprietary, high performance SuperFlash technology. The SST32HF16x1/32x1 devices use a PseudoSRAM. The SST32HF16x1C/32x1C devices use standard SRAM.

FEATURES:

• ComboMemories organized as:

– SST32HF1621C: 1M x16 Flash + 128K x16 SRAM

– SST32HF1641x: 1M x16 Flash + 256K x16 SRAM

– SST32HF1681: 1M x16 Flash + 256K x16 SRAM

– SST32HF3241x: 2M x16 Flash + 256K x16 SRAM

– SST32HF3281: 2M x16 Flash + 512K x16 SRAM

• Single 2.7-3.3V Read and Write Operations

• Concurrent Operation

– Read from or Write to SRAM while Erase/Program Flash

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 15 mA (typical) for Flash or SRAM Read

– Standby Current:

- SST32HFx1: 60 µA (typical)

- SST32HFx1C: 12 µA (typical)

• Flexible Erase Capability

– Uniform 2 KWord sectors

– Uniform 32 KWord size blocks

• Erase-Suspend/Erase-Resume Capabilities

• Security-ID Feature

– SST: 128 bits; User: 128 bits

• Hardware Block-Protection/WP# Input Pin

– Bottom Block-Protection (bottom 32 KWord)

• Fast Read Access Times:

– Flash: 70 ns

– SRAM: 70 ns

• Latched Address and Data for Flash

• Flash Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 40 ms (typical)

– Word-Program Time: 7 µs (typical)

• Flash Automatic Erase and Program Timing

– Internal VPP Generation

• Flash End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard Command Set

• Package Available

– 63-ball LFBGA (8mm x 10mm x 1.4mm)

– 62-ball LFBGA (8mm x 10mm x 1.4mm)

• All non-Pb (lead-free) devices are RoHS compliant