SR6P7C4中文资料意法半导体数据手册PDF规格书

特性 Features

• AEC-Q100 automotive qualification on going

• SR6 integration MCUs:

– Have superior real-time and safe performance (with highest ASIL-D

capability)

– Bring HW based virtualization technology to MCUs for simplified multiple

SW integrations at optimized performance

– Have built-in fast and cost effective OTA reprogramming capability (with

built-in dual image storage)

– Offer high speed security cryptographic services, for example for

network authentication

Cores

• 32-bit Arm® v8-R compliant CPU cores:

– 6 Cortex®‑R52+ cores (4 of them with checker cores, 2 in split-lock

configuration) allowing usage as either 6 cores (4 of them in lockstep

configuration) or 5 cores (all of them in lockstep configuration), single

precision FPU, new privilege level for real-time virtualization

– 2 NEON extensions (for example SIMD, dual precision FPU)

• 2 Cortex®‑M4 multipurpose accelerators (data move and [pre]-processing).

One in lockstep configuration

• 4 eDMA engines in lockstep configuration

Memories

• Up to 20 MB on-chip NVM non-volatile memory:

– PCM (phase change memory) as non-volatile memory

– 19.5 MB code NVM, with embedded memory replication for OTA (overthe-

air) reprogramming with up to 2x 19.5 MB

– 512 KB HSM dedicated code NVM

• 640 KB data NVM (512 KB + 128 KB dedicated to HSM)

• Up to 8400 KB on-chip general-purpose SRAM

Security: hardware security module - 2nd generation

• On-chip high-performance security module with EVITA full support

• Symmetric and asymmetric cryptography processor

• High performance lock-stepped AES-light security sub-system for fast ASIL-D cryptographic services

Safety: comprehensive new generation ASIL-D safety concept

• New state-of-the-art safety measures at all levels of the architecture for most efficient implementation of

ISO26262 ASIL-D functionalities

• Complete HW virtualization architecture built on Cortex®‑R52+ new privilege mode (best-in class SW

isolation, real-time support for multiple virtual machine/applications)

Peripheral, IOs, communication interfaces

• 11 LINFlexD modules

• 2 dual-channel FlexRay controllers

• 10 queued serial peripheral interface (SPIQ) modules

• 4 microsecond channels (MSC) and 2 microsecond plus (MSC-Plus) channels

• 2 SENT modules (15 channels each)

• 2 PSI5 modules (1 channel each)

• Enhanced analog-to-digital converter system with:

– 12 separate 12-bit SAR analog converters (including one supervisor/safety ADC).

– 4 separate 9-bit SAR analog converters (2 channels each) with fast comparator mode

– 12 separate 16-bit sigma-delta analog converter with embedded DSP processor on each SD ADC

– Enhanced interconnection with GTM timer for autonomous ADC/GTM subsystem operation

• Advanced timed I/O capability:

– Generic timer module (GTM4154)

– High-resolution timer

• Communication interfaces:

– 2 ethernet controllers 10/100/1000 Mbps, compliant with IEEE 802.3-2008: IPv4 and IPv6 checksum

modules, AVB, VLAN and EMC optimized SGMII

– 11 modular controller area network (MCAN) modules, and 1 time-triggered controller area network

(M-TTCAN), all supporting flexible data rate (ISO CAN-FD)

– 2 CAN-XL interfaces

External memory interfaces

• 2 OctoSPI to support HyperBus™ memory (Flash/RAM) devices

描述 Description

Stellar integration MCUs have been designed to meet the requirements of domain controllers and ECUs with

high integration requested in the architectures of connected update-able automated and electrified cars. They

have superior real-time and safe performance (with highest ASIL-D capability). Bringing HW based virtualization

technology to MCUs, they ease the development and integration of multiple source SW onto the same HW while

maximizing the resulting SW performance. They offer high efficiency OTA reprogramming capability with fast new

image download and activation at almost no memory overhead thanks to SR6 unique built-in dual image storage

tailored to OTA reprogramming needs and provide high speed security cryptographic services, for instance for

network authentication.