SPC5674FF3MVR3中文资料恩XP数据手册PDF规格书

• Dual issue, 32-bit CPU core complex (e200z7)

– Compliant with the Power Architecture® embedded

category

– 16 KB I-Cache and 16 KB D-Cache

– Includes an instruction set enhancement allowing

variable length encoding (VLE), optional encoding of

mixed 16-bit and 32-bit instructions, for code size

footprint reduction

– Includes signal processing extension (SPE2) instruction

support for digital signal processing (DSP) and

single-precision floating point operations

• 4 MB on-chip flash

– Supports read during program and erase operations, and

multiple blocks allowing EEPROM emulation

• 256 KB on-chip general-purpose SRAM including 32 KB

of standby RAM

• Two direct memory access controller (eDMA2) blocks

– One supporting 64 channels

– One supporting 32 channels

• Interrupt controller (INTC)

• Frequency modulated phase-locked loop (FMPLL)

• Crossbar switch architecture for concurrent access to

peripherals, flash, or RAM from multiple bus masters

• External bus interface (EBI) for calibration and application

development (not available on all packages)

• System integration unit (SIU)

• Error correction status module (ECSM)

• Boot assist module (BAM) supports serial bootload via

CAN or SCI

• Two second-generation enhanced time processor units

(eTPU2) that share code and data RAM.

– 32 standard channels per eTPU2

– 24 KB code RAM

– 6 KB parameter (data) RAM

• Enhanced modular input output system supporting 32

unified channels (eMIOS) with each channel capable of

single action, double action, pulse width modulation

(PWM) and modulus counter operation

• Four enhanced queued analog-to-digital converters

(eQADC)

– Support for 64 analog channels

– Includes one absolute reference ADC channel

– Includes eight decimation filters

• Four deserial serial peripheral interface (DSPI) modules

• Three enhanced serial communication interface (eSCI)

modules

• Four controller area network (FlexCAN) modules

• Dual-channel FlexRay controller

• Nexus development interface (NDI) per IEEE-ISTO

5001-2003/5001-2008 standard

• Device and board test support per Joint Test Action Group

(JTAG) (IEEE 1149.1)

• On-chip voltage regulator controller regulates supply

voltage down to 1.2 V for core logic