SPC564B64L8中文资料用于汽车车身和网关应用的32位Power Architecture MCU数据手册ST规格书

描述 Description

The SPC564Bxx and SPC56ECxx is a new family of next generation microcontrollers built on the Power Architecture embedded category. This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device.

The SPC564Bxx and SPC56ECxx family expands the range of the SPC560B microcontroller family. It provides the scalability needed to implement platform approaches and delivers the performance required by increasingly sophisticated software architectures. The advanced and cost-efficient host processor core of the SPC564Bxx and SPC56ECxx automotive controller family complies with the Power Architecture embedded category, which is 100 percent user-mode compatible with the original Power Architecture user instruction set architecture (UISA). It operates at speeds of up to 120 MHz and offers high performance processing optimized for low power consumption. It also capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations.

特性 Features

• e200z4d, 32-bit Power Architecture®
•up to 120 MHz and 200 MIPs operation
•up to 80 MHz and 75 MIPs operation
•Up to 3 MByte on-chip Flash with ECC
•Up to 256 KByte on-chip SRAM with ECC
•64KByte on-chip Data Flash with ECC
•16-entry memory protection unit (MPU)
•User selectable Memory BIST
•255 interrupt sources with 16 priority levels
•Up to 54 ext. IRQ including 30 wake-up
• System timer units
•8-ch. 32-bit periodic interrupt timer (PIT)
•4-channel 32-bit system timer (STM)
•Safety System Watchdog Timer (SWT)
•Real-time clock timer (RTC/API)
•Up to 64 channels with PWM/MC/IC/OC
•Up to 62 channels extendable to 90 ch.
•Multiple Analog Watchdog
•Advanced shiffted PWM generation
•ADC conversion synchronized on PWM
• Communication interfaces
•Up to 6 FlexCAN with 64 buffers each
•Up to 10 LINFlex/UART channels
•Up to 8 buffered DSPI channels
•I2C interface
•One FleyRay (dual-ch.) with 128 buffers
•Fast Ethernet Controller
•AES-128 en/decryption, CMAC auth.
•Secured device boot mode
• Clock generation
•4 to 40 MHz main oscillator
•16 MHz internal RC oscillator
•Software-controlled FMPLL
•128 kHz internal RC oscillator
•32 kHz auxiliary oscillator
•Clock Monitoring Unit (CMU)
•Ultra low power STANDBY
•CAN Sampler to store CAN ID in STBY
•Fast wake-up and exectute from RAM
•Nexus 3+ interface on LBGA256 only
•Nexus 1 on all devices
•Single 5 V or 3.3 V supply
•On-chip Vreg with external ballast transitor
• Operating temperature range -40 to 125 °C