SPC564A70B4中文资料32-bit Power Architecture MCU for Automotive Powertrain Applications数据手册ST规格书

描述 Description

This microcontroller is a 32-bit system-on-chip (SoC) device intended for use in mid-range engine control and automotive transmission control applications.
It is compatible with devices in ST's SPC56xx family and offers performance and capability above that of the SPC563M devices.
The microcontroller's e200z4 host processor core is built on the Power Architecture technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP).
The device has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by a 128 KB on-chip SRAM and a 2 MB internal flash memory.
For development, the device includes a calibration bus that is accessible only when using the STMicroelectronics calibration tool.

特性 Features

• 150 MHz e200z4 Power Architecture®core
• Superscalar architecture with 2 execution units
• Up to 4 multiply and accumulate operations per cycle
• 2 MB on-chip flash memory with ECC and read-while-write (RWW)
• 8 KB instruction cache (with line locking), configurable as 2- or 4-way
• 4 x 4 crossbar switch (XBAR)
• Fail Safe Protection
• CRC unit with 3 submodules
• Interrupt
• 64-channel eDMA
• 3 eSCI modules
• 3 FlexCAN modules with 64 message buffers each
• 1 eMIOS (24 unified channels)
• 32 standard channels
• 2 enhanced queued analog-to-digital converters (eQADCs)
• 688 ns minimum conversion time
• Nexus: Class 3+ for core; Class 1 for eTPU
• Development Trigger Semaphore (DTS)
• On-chip 4-40 MHz main oscillator
• Up to 112 general purpose I/O lines
• Flexible supply scheme
• Multiple external supply: 5 V, 3.3 V , and 1.2 V
• Designed for LQFP176, LBGA208, PBGA324