SPC5645SF1VLT

NXP 32-bit MCU, Power Arch core, 2MB Flash, 125MHz, -40/+105degC, Automotive Grade, QFP 208; • Dual-issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z4d) Memory management unit and 4 KB instruction cache\n• Variable length encoding (VLE) instruction set enables significant code size reduction over conventional Book E-compliant code\n• Up to 2 MB on-chip flash with flash controller\n• Separate 4 x 16 KB flash block for EEPROM emulation\n• Up to 64 KB on-chip SRAM with ECC\n• Up to 1 MB on-chip graphics SRAM (no ECC)\n• Two TFT displays up to WVGA resolution parallel data interface (PDI) for digital video input\n• Sound generation and playback using PCM or DDS sources with 4-channel mixer and PWM or I2S outputs\n• Stepper motor drivers with stepper stall detect for up to six gauges\n;

The NXP® MPC564xS family of MCUs targets the needs of automotive instrument cluster and industrial markets.\nIncludes on-chip display control units that directly drives the TFT displays\nLow-power design enables dynamic power management of core and peripherals\nOffers an industry standard graphics accelerator to help drive sophisticated graphics (e.g., simulated instrument cluster needles or image warping for heads-up displays)\nOffers code compatibility with applications in the MPC560xS environment\nSupported by robust enablement ecosystem to simplify and accelerate development\n